Semiconductor devices, microelectronic devices, and other microfeature devices are typically manufactured on a workpiece having a large number of individual dies (e.g., chips). Each wafer undergoes several different procedures to construct the switches, capacitors, conductive interconnects and other components of a device. For example, a workpiece can be processed using lithography, implanting, etching, deposition, planarization, annealing, and other procedures that are repeated to construct a high density of features. One aspect of manufacturing microelectronic devices is forming dielectric layers at several different levels throughout the manufacturing process.
Dielectric layers are one of the primary components in integrated circuits. For example, high-k dielectric layers are used as the gates in transistors, and low-k dielectric layers are used to separate interconnect lines arranged in several levels of a microelectronic workpiece. Dielectric layers can also be used as masks in the fabrication processes, passivation layers, and/or cap layers. Dielectric layers are often formed by depositing a uniform layer of dielectric material, which has a matrix material that may be doped with some atoms or molecules. In several applications, the matrix material can be transformed using an activation energy, such as thermal energy, ultraviolet energy, or e-beam energy, to form pores within the matrix material. Nanoglass is also a porous dielectric material, but it is fabricated by a different process.
One aspect of manufacturing microelectronic devices is ascertaining certain properties of the dielectric layers. For example, the dielectric constant must be within a desired range for the dielectric layers to function properly. In the case of interlayer dielectrics or inter-metallization dielectric layers, it is typically desirable to have a lower k value to enable high-speed operation of the integrated circuits. For transistor gates, however, a higher k value is desired. The dielectric layers should also have a desired elasticity and hardness because if they are too hard or too soft they can compromise the performance of other fabrication processes. A soft dielectric layer, for example, may be crushed in subsequent chemical-mechanical planarization, cleaning, and/or packaging processes. As a result, it is necessary to evaluate the properties of the dielectric layers at several stages throughout fabricating integrated circuits.
One challenge of fabricating integrated circuits, however, is that conventional techniques for measuring properties of the dielectric layers may be inconvenient and may damage the wafers. For example, the DC (or RF) dielectric constant is conventionally measured by contacting the dielectric layer with an electrode and applying an electrical signal across the dielectric layer. The contact of the electrode may damage or contaminate the wafer. Similarly, the Young's Modulus and the hardness of the dielectric layer are conventionally measured using nano-tip indents that may similarly damage or contaminate the wafer. Therefore, it would be desirable to develop a non-contact method that measures a property of a dielectric layer using a suitable type of energy.